The present invention is directed to a manufacturing method for a self-aligned through hole of an integrated semiconductor circuit having track-shaped structures arranged on a semiconductor substrate. The through hole at least partially exposes a more deeply disposed, conductive region situated between two track-shaped structures. The invention is also directed to a semiconductor structure having track-shaped structures on a semiconductor substrate and having a more deeply disposed region arranged between the track-shaped structures.
It is often necessary when manufacturing integrated circuits to produce contacts between different conductive structures, for example an upper interconnect and a more deeply disposed, conductive region. As a consequence of the increasing miniaturization of the lateral dimensions of all structures on the semiconductor substrate, such contacts are preferably manufactured in self-aligned fashion, i.e. the actual contact area is not lithographically defined but is defined by structures that already exist. In many instances, however, a photoresist mask with a correspondingly complicated process management cannot be completely eliminated even in the manufacture of a self-aligned through hole. The adjustment or alignment of this photoresist mask, however, is relatively uncritical.
An example of this is the manufacture of a self-aligned contact between a bit line and a more deeply disposed source/drain region of a transistor in a DRAM circuit. The through hole is thereby arranged between source/drain region and the word line provided with an oxide encapsulation.
As set forth in the article by Kuesters et al., Symposion in VLSI Technology 1987, Japan, pages 93-94, a self-aligned through hole can be manufactured in that an oxide/nitride/oxide triple layer is applied surface-wide after the oxide encapsulation and is in turn removed over the conductive region using a phototechnique in a plurality of etching processes, whereby the nitride layer serves as an etching stop. The through hole in the photomask is thereby larger than the actual contact area that is essentially defined by the oxide encapsulation.
One disadvantage of this so-called FOBIC process is that the necessary nitride layer produces mechanical stresses that can cause offsets in the proximity of the word lines. Further, problems can arise in the structuring of the bit line in relationship to the etched edge of the upper oxide layer. When the bit line edge lies approximately over this etched edge, erect filaments of the bit line material can result that can cause short-circuits. When, by contrast, the etched edge is not overlapped by the bit line, an unbeneficial topography is obtained. A further disadvantage is that the upper oxide layer can only be moderately doped because of the wet-etching process, as a result whereof a planarization in a later flow step is limited.